The invention relates to a semiconductor integrated circuit device, and more particularly to a bipolar complementary metal oxide semiconductor (Bi-CMOS) integrated circuit device and a method of fabricating the same.
The Bi-CMOS integrated circuit device includes a bipolar transistor and a complementary metal oxide field effect transistor (CMOS), both of which are formed in a single semiconductor substrate. The complementary metal oxide field effect transistor (CMOS) comprises a pair of an n-channel type metal oxide field effect transistor (n-MOS) and a p-channel type metal oxide field effect transistor (p-MOS). In general, a bipolar transistor has a superior property in high frequency and high speed performances. In contrast, a CMOS transistor has a superior property in a low power consumption. The bipolar-CMOS integrate circuit device is so designed that the bipolar transistor and the CMOS transistor are respectively formed on a signal semiconductor substrate. This permits the bipolar-CMOS integrated circuit device to exhibit both a high frequency performance property possessed by the bipolar trnasistor and a low power consumption property possessed by the CMOS transistor. Namely, the bipolar-CMOS integrated circuit device possesses such respective superior properties of the bipolar transistor and the COMS transistor.
Further, in view of reduction of fabrication processes of the bipolar CMOS integrated circuit device, it is required to fabricate the bipolar transistor and the CMOS transistor in the same process.
FIG. 1 illustrates a structure of the conventional bipolar-CMOS integrated circuit device in which a p-channel MOS transistor and an n-p-n bipolar transistor only are illustrated and thus an illustration of an n-channel MOS transistor is omitted. Previous to a description of fabrication processes, the structure of the conventional bipolar-CMOS integrated circuit device will be described with reference to FIG. 1.
The bipolar-CMOS integrated circuit device has a semiconductor substrate 1. A p-channel type MOS transistor region 10C, an n-p-n bipolar transistor region 101 and a PG,4 resistive region 102 are formed on the semiconductor substrate. A plurality of n-type buried layers 2 doped with an n-type dopant are formed on the semiconductor substrate 1 in each of the p-channel type MOS transistor region 100, the bipolar transistor region 101 and the resistive region 102. Further, a p-type buried layer 3 doped with a p-type dopant is formed on the semiconductor substrate 1 at boundary areas between the p-channel MOS transistor region 100 and the bipolar transistor region 101 and between the bipolar transistor region 101 and the resistive region 102. An n-type epitaxial layer 4 is formed on the n-type buried layer 2 in the bipolar transistor region 101. An n-type well region 6 is formed on the n-type buried layer 2 in the p-channel MOS transistor region 100. A p-type well region 5 is formed on the p-type buried layer 3 at the boundary area between the p-channel MOS transistor region 100 and the bipolar transistor region 101. Further, a chennel stopper 7 is formed on the p-type well region 100 at the boundary area between the p-channel MOS transistor region 100 and the bipolar transistor region 101. Furthermore, field oxide films 8 serving as isolation films are formed on the channel stopper 7 to isolate between the p-channel MOS transistor region 100 and the bipolar transistor region 101.
In the p-channel MOS transistor region 100, source and drain regions doped with a p-type dopant are formed at upper portions of the n-type well region 6 thereby defining p-type channel region. A gate oxide film is formed on the channel region. A gate contact is formed on the gate oxide film. Side-wall oxide films are formed at opposite side portions of the gate contact 11. A first inter-layer insulator is formed on the entire surface of the device. A second inter-layer insulator 20 is further formed on the first inter-layer insulator 19. Source and drain contacts 24-1 and 24-2 are so formed as to be in contact with the source and drain regions respectively.
In the bipolar transistor region 101, an.sup.+ -type low resistive buried layer is formed directly under a collector contact region. A collector contact 24-5 is formed on the n.sup.+ -type low resistive buried layer. The existence of the n.sup.+ -type low resistive buried layer makes a collector resistance reduced as its high dopant concentration thereby permitting the bipolar transistor to exhibit a high frequency property. Side-wall oxide films are formed at opposite side portions of the collector contact 24-5. A p-type base region and a graft base region are formed at upper portions of the n-type epitaxial layer 4. A base contact 24-3 is so formed as to be in contact with the graft base region. An emitter region is formed in an upper portion of the base region. An emitter contact 24-4 is so formed as to be in contact with the emitter region. A device performance depends upon the active base region but for the graft base region. The graft base region has a higher dopant concentration than a dopant concentration of the active base region as being independent from a device performance, thereby making a base resistance reduced.
The conventional fabrication processes of the bipolar-CMOS integrated circuit device will be described in reference to FIGS. 1 and 2A to 2D.
The semiconductor substrate 1 is prepared, after which n-type buried layers 2 doped with an n-type dopant are formed by a normal process on the semiconductor substrate 1 in each of the p-channel type MOS transistor region 100, the bipolar transistor region 101 and the resistive region 102. Further, the p-type buried layer 3 doped with a p-type dopant is formed by a normal process on the semiconductor substrate 1. The n-type epitaxial layer 4 is formed by a normal process on the n-type buried layer 2 in the bipolar transistor region 101. The n-type well region 6 is formed on the n-type buried layer 2 in the p-channel MOS transistor region 100. A p-type well region 5 is formed on the p-type buried layer 3. Further, the channel stopper 7 is formed on the p-type well region 100. Furthermore, field oxide films 8 serving as isolation films are formed on the channel stopper 7 to isolate between the p-channel MOS transistor region 100 and the bipolar transistor region 101. Subsequently, as illustrated in FIG. 2A, a thin oxide film 9 having a thickness in the range from 150 angstroms to 400 angstroms is formed on each of the p-channel MOS transistor region 100. the bipolar transistor region 101 and the resistive region 102, in addition to a collector contact region 10. The above processes are normal processes which are well known in the art.
As illustrated in FIG. 2B, after removing selectively a portion of the thin oxide film 9 in the collector contact region 10, a polycrystalline silicon film doped with an n-type dopant at a high dopant concentration is so selectively formed as to remain at a gate contact region and a collector contact region 10. A portion of the polycrystalline silicon film remaining in the collector contact region 10 is in contact with the n.sup.+ -type buried layer 13 thereby resulting in a formation of the collector contact 12. In contrast, a portion of the polycrystalline silicon film remaining in the gate contact region serves as a gate contact 11.
As shown in FIG. 2C, a selective ion-implantation of an n-type dopant into an n-channel MOS transistor region is accomplished at a dopant concentration in the range from 1.times.10.sup.17 atoms/cm.sup.3 to 5.times.10.sup.18 atoms/cm.sup.3. Also, a selective ion-implantation of but a p-type dopant into the p-channel MOS transistor region 100 is accomplished at a dopant concentration in the range from 5.times.10.sup.17 atoms/cm.sup.3 to 2.times.10.sup.18 atoms/cm.sup.3. As a result, p-type source and drain regions 14-1 and 14-2 having a relatively low dopant concentration are formed in the p-channel MOS transistor region 100 thereby defining the channel region under the gate contact 11. Further, the p-type base region 15 having a relatively low dopant concentration is formed in the bipolar transistor region 101. Furthermore, the p-type resistive region 25 are formed in the resistive region 102.
A vapor phase growth oxide film having a thickness in the range from 100 nanometers to 300 nanometers is formed on an entire surface of the device. After that, an anisotropic etching to the vapor phase growth oxide film is accomplished by using a gas such as CF.sub.4 so that the vapor phase growth oxide film remains at only opposite side portions of each of the gate contact 11 and the collector contact 12. As a result, side-wall oxide films 16 are formed at opposite side portions of each of the gate contact 11 and the collector contact 12 respectively.
In addition, a selective ion-implantation of an n-type dopant into the n-channel MOS transistor region is accomplished at a dopant concentration of approximately 1.times.10.sup.20 atoms/cm.sup.3. Also, a selective ion-implantation of but a p-type dopant into the p-channel MOS transistor region 100 is accomplished at a dopant concentration in the range from 1.times.10.sup.19 atoms/cm.sup.3 to 2.times.10.sup.20 atoms/cm.sup.3. As a result, p-type source and drain regions 17-1 and 17-2 having a relatively high dopant concentration are formed in the p-channel MOS transistor region 100. Further, the p-type graft base region 18 having a relatively high dopant concentration is formed in the bipolar transistor region 101. Furthermore, a p-type low resistive portions 26 are formed in the resistive region 102.
Subsequently, as illustrated in FIG. 2D, the first inter-layer insulator 19 having a thickness in the range from 150 nanometers to 300 nanometers is formed by a vapor phase growth method on an entire surface of the device. After that, an opening as selectively formed on the first inter-layer insulator 19 over the base region 15. A second polycrystalline silicon film doped with an n-type dopant is selectively formed in the vicinity of the opening so as to be in contact with the p-type base region 15, followed by a diffusion of the n-type dopant from the second polycrystalline silicon film into the base region. As a result, the n-type emitter region 21 is formed at an upper portion of the base region 15.
As shown in FIG. 1, a second inter-layer insulator 22 having a thickness in the range from 300 nanometers to 700 nanometers is formed on an entire surface of the device, followed by a selective formation of openings. Further, a metal film made of a metal having a low conductivity such as aluminium is so formed on the second inter-layer insulator 22 as to cover the openings formed in the second inter-layer insulator 22. Namely, the openings formed in the second inter-layer insulator 22 are respectively filled with the metal film. The metal film is so patterned as to remain in the vicinity of the respective openings. The remaining portions of the metal film serve as respective contacts, and thus the source and drain contacts 24-1 and 24-2 in the p-channel MOS transistor region 100 and the base, emitter and collector contacts 24-3, 24-4 and 24-5 in the bipolar transistor region 101, in addition contacts in the resistive region 102. The bipolar-CMOS integrated circuit device has been formed by such processes.
The conventional bipolar-CMOS integrated circuit device is, however, engaged with the following disadvantages, which will be described in detail.
As described above, in the process illustrated in FIG. 2B, the vapor phase growth oxide film was formed on the entire surface of the device, followed by the anisotropic etching of the vapor phase growth film. As a result, the vapor phase growth oxide film remains at only opposite side portions of each of the gate contact 11 and the collector contact 12. In this process, the bipolar transistor region 101 is also subjected to the anisotropic etching. The anisotropic etching process provides a damage to the active base region 15. The anisotropic etching process also causes crystal defects to be generated in the active base region 15. In such a case, the emitter region 21 is forced to overlay such base region 15 having a damage or crystal defects. The existence of the damaged portion or the crystal defects makes an emitter-base junction exhibit the short-circuit. This makes a yield of the device reduced.
To combat of the above disadvantages, the following method has been proposed. In the process illustrated in FIG. 2B, after forming the vapor phase growth oxide film on the entire surface of the device, a photo-resist 27-2 is provided so selectively as to exist over the emitter region by using a photo-lithography as illustrated in FIG. 3A. After that, the anisotropic etching to the vapor phase growth oxide film is accomplished to form the side-wall oxide films 16. Thus, the photo-resist 27-2 which covers a portion of the active base region 15 is able to keep the covered portion of the active base region 15 from suffering any damage provided by the the anisotropic etching process. A portion of the active base region which is not covered with the photo-resist 27-2, however, suffers any damage provided by the anisotropic etching to the vapor phase growth oxide film. The existence of the photo-resist 27-2 prevents crystal defects to be caused in the active base region 15. This makes the emitter-base junction free from the short-circuit.
After the anisotropic etching process, the vapor phase growth oxide film remains at a portion which is covered with the photo-resist 27-2. Then, an ion-implantation of an n-type dopant into the n-channel MOS region is accomplished at a high dopant concentration.
As illustrated in FIG. 3B, the photo-resist 27-2 is removed, after which a photo-resist 27-3 is so selectively provided as to cover the remaining portion of the vapor phase growth oxide film. The photo-resist 27-3 also covers an exposed portion of the active base region 15, but for a region in which the graft base region 18 will be formed. Further, in the resistive region, a photo-resist is so selectively as to cover the p-type resistive region 25, but for the low resistive portions 26. A selective ion-implantation of a p-type dopant into the p-channel MOS transistor region is accomplished at a high dopant concentration by using the photo-resist 27-3 as a mask. As a result, the graft base region 18 having a high dopant concentration is formed at the portion of the base region which is not covered with the photo-resist 27-3. Thus, an edge portion of the photo-resist 27-3 defines the boundary between the graft base region 18 and the base region 15. The above ion-implantation of the p-type dopant also forms the source and drain regions 17-1 and 17-2 in the p-channel MOS transistor region 100, in addition the resistive plug portions 26 in the resistive region 102.
As shown in FIG. 3C, after removing the photo-resist 27-3, the first inter-layer insulator 19 is formed on an entire surface of the device, after which an opening is selectively formed in the inter-layer insulator 19. A second polycrystalline silicon film doped with an n-type dopant is so selectively formed as to fill the opening in the first inter-layer insulator 19 thereby resulting in a formation of an emitter contact 20.
With respect to the base region 15 in the bipolar transistor region 101, as described above, the portion of the base region 15 underlying the remaining vapor phase growth oxide film 23 is free from any damage provided by the anisotropic etching as being covered with the photo-resist 27-2 in the anisotropic etching process. In contrast, a portion 28 of the base region 15 which does not underlay the remaining vapor phase growth oxide film 23, however, suffers any damage provided by the anisotropic etching. Namely, the damaged portion 28 of the base region 15 exists between the undamaged portion of the base region 15 underlying the remaining vapor phase growth oxide film 23 and the graft base region 18. The damaged portion 28 has a length in the range from 0.2 micrometers to 2.0 micrometers. A surface of the damaged portion 28 is etched by the anisotropic etching to the vapor phase growth oxide film. This makes a base resistance increased but only in the damaged portion 28 of the base region 15. The increase of the base resistance in the damaged portion 28 renders the high frequency property possessed by the bipolar transistor deteriorative considerably.
The damaged portion 28 of the active base region 15 formed in the the conventional fabrication process makes it difficult that the bipolar-CMCS integrated circuit device exhibits an excellent high frequency performance. It is therefore required to develop a novel fabrication method of the bi-CMOS integrated circuit device having a base region and an emitter region, both of which are free from any damage provided by the anisotropic etching for forming the side-wall oxide films 16.
Similarly, the resistive region 102 is also engaged with disadvantages in any damage provided by the anisotropic etching to the vapor phase growth oxide film. In the anisotropic etching process, since the p-type resistive region 25 was not covered by a photo-resist, the resistive region 25 suffers such damage that a surface of the p-type resistive region 25 is etched by the anisotropic etching. The etching of the surface of the p-type resistive region 25 makes the resistance thereof variable. The variation of the resistance possessed by the p-type resistive region 25 depends upon the magnitude of the etching of the p-type resistive region 25. The conventional fabrication method makes it difficult that the resistance of the p-type resistive region 25 possesses a high accuracy. It is also require to develop a novel fabrication method of the Bi-CMOS integrated circuit device having a resistive region being free from any damage provided by the anisotropic etching for forming the side-wall oxide films 16.